As flat-panel displays in which thin-film transistors driven by an active matrix method are used, a liquid crystal display, a plasma display, an organic EL display, an inorganic EL display, and the like are known. In these flat panel displays in which the thin-film transistors are used, wires made of a metallic layer are formed to adhere to the surface of a glass substrate in a grid pattern, and thin film transistors are provided at the intersections of the grid-pattern wires made of the metallic layer.
As exemplified in a schematic vertical cross-sectional view of main portions in FIG. 1, it is well known that the thin film transistor has a laminate structure which includes a gate electrode layer 3 of pure copper joined through an adhesion layer 2 of metallic Mo, a gate insulating layer 4 of silicon nitride, an Si semiconductor layer 5, n-type Si semiconductor layers 6, barrier layers which are formed by sputtering in an oxidizing atmosphere using a Cu alloy target, a wire layer 9 composed of a pure copper drain electrode layer 9a and a source electrode layer 9b which are partitioned by an isolation trench 8, a passivation layer of silicon nitride, and a transparent electrode layer. The layers are laminated in series on the surface of a glass substrate 1, and the passivation layer and the transparent electrode layer are not shown in FIG. 1.
In a process of manufacturing a thin film transistor having such a laminate structure, the isolation trench 8 is formed in the wire layer 9 by a wet etching treatment so as to divide the wire layer 9 into the drain electrode layer 9a and the source electrode layer 9b. Then, a portion of the n-type Si semiconductor layer which is exposed at the bottom of the diffusion groove (isolation trench 8) formed in the wire layer 9 is removed by a dry etching treatment.
In the portion of the Si semiconductor layer 5 exposed at the bottom of the isolation trench 8 after the wet etching treatment and the dry etching treatment, hydrogen atoms are removed from the surface by the dry etching treatment. Thereby, the surface becomes extremely unstable, that is, the number of dangling bonds increases, and these dangling bonds become surface defects. The surface defects increase an off-state current of the thin film transistor. As a result, an unstable state is formed in which problems such as a decrease in the contrast of an LCD, a reduction in a viewing angle, and the like cannot be avoided. Therefore, hydrogen plasma processing is performed on the exposed surface of the Si semiconductor layer 5 under the conditions where 100% of hydrogen gas is used, a hydrogen gas flow rate is in a range of 10 to 1000 SCCM, a hydrogen gas pressure is in a range of 10 to 500 Pa, a processing temperature is in a range of 200 to 250° C., an output is in a range of 0.005 to 0.5 W/cm2, and a processing time is in a range of 0.5 to 1 minute. Thereby, the dangling bonds of the surface of the Si semiconductor layer 5 are bound to hydrogen atoms to stabilize the surface thereof.
In addition, it is also known that the barrier layers which are constituting layers of the thin film transistor are formed by the following method: a film is formed by sputtering with a Cu alloy sputtering target having a component composition which includes, in terms of atomic % (hereinafter ‘%’ indicates ‘atomic %’), one or more of Mg, Ti, Al, and Cr: 0.5% to 20% with the balance being Cu and inevitable impurities (1% or less); and then the film is subjected to a heating oxidation treatment in an oxidizing atmosphere (air).
Meanwhile, large-sized screens and high integration of various types of flat-panel displays have been developed remarkably in recent years, and with this development, much higher adhesion strength tends to be required between each of the laminated films included in the thin-film transistor.
In the above-mentioned conventional thin-film transistor, high adhesion strengths capable of sufficiently satisfying the above-mentioned requirement are secured between the glass substrate 1 and the gate electrode layer 3 of pure copper, between the gate electrode layer 3 and the gate insulating layer 4 of silicon nitride, between the gate insulating layer 4 and the Si semiconductor layer 5, between the Si semiconductor layer 5 and the n-type Si semiconductor layers 6, between the barrier layers and the wire layer 9 of pure copper, between the wire layer 9 of pure copper and the passivation layer of silicon nitride, and between the passivation layer and the transparent electrode layer. The passivation layer and the transparent electrode layer are not shown. However, the adhesion strength between the barrier layer and the n-type Si semiconductor layer 6 is relatively low, and the adhesive strength therebetween is not high enough to satisfy the above-mentioned requirement.